
Atomera Incorporated Common Stock
ATOM
ATOM: Atomera Inc is engaged in the business of developing, commercializing, and licensing proprietary processes and technologies for the semiconductor industry. The mears silicon technology of the company can be used for applications like Analog, DRAM, FinFET technology, logic and processors, and SRAM.
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New patents grants
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Patent Title: Methods for making radio frequency (rf) semiconductor devices including a ground plane layer having a superlattice Aug. 29, 2023
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Patent Title: Semiconductor device including superlattice with o Aug. 15, 2023
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Patent Title: Method for making semiconductor device with selective etching of superlattice to accumulate non-semiconductor atoms Aug. 08, 2023
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Patent Title: Method for making semiconductor device including superlattice with o18 enriched monolayers Jun. 20, 2023
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Patent Title: Method for making an inverted t channel field effect transistor (itfet) including a superlattice May. 30, 2023
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Patent Title: Vertical semiconductor device with enhanced contact structure and associated methods May. 30, 2023
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Patent Title: Method for making semiconductor device with selective etching of superlattice to define etch stop layer Apr. 18, 2023
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Patent Title: Method for making semiconductor device including a superlattice and providing reduced gate leakage Jan. 31, 2023
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Patent Title: Semiconductor device including a superlattice and providing reduced gate leakage Oct. 11, 2022
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Patent Title: Bipolar junction transistors including emitter-base and base-collector superlattices Sep. 06, 2022
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Patent Title: Methods for making bipolar junction transistors including emitter-base and base-collector superlattices Sep. 06, 2022
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Patent Title: Method for making superlattice structures with reduced defect densities Aug. 30, 2022
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Patent Title: Vertical semiconductor device with enhanced contact structure and associated methods Jul. 12, 2022
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Patent Title: Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice Jun. 07, 2022
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Patent Title: Semiconductor device including a superlattice and an asymmetric channel and related methods May. 10, 2022
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Patent Title: Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers Apr. 12, 2022
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Patent Title: Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods Nov. 23, 2021
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Patent Title: Semiconductor device including a superlattice with different non-semiconductor material monolayers Nov. 16, 2021
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Patent Title: Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods Aug. 17, 2021
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Patent Title: Method for making a semiconductor device including a superlattice within a recessed etch Jul. 27, 2021
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Patent Title: Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices Mar. 02, 2021
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Patent Title: Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices Mar. 02, 2021
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Patent Title: Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice Jan. 05, 2021
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Patent Title: Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice Dec. 29, 2020
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Patent Title: Method for making a semiconductor device including enhanced contact structures having a superlattice Dec. 29, 2020
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Patent Title: Method for making a varactor with hyper-abrupt junction region including a superlattice Dec. 15, 2020
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Patent Title: Method for making a finfet including source and drain dopant diffusion blocking superlattices to reduce contact resistance Dec. 01, 2020
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Patent Title: Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance Nov. 24, 2020
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Patent Title: Varactor with hyper-abrupt junction region including a superlattice Nov. 17, 2020
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Patent Title: Method for making a finfet having reduced contact resistance Nov. 17, 2020
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Patent Title: Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods Nov. 17, 2020
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Patent Title: Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance Nov. 17, 2020
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Patent Title: Varactor with hyper-abrupt junction region including spaced-apart superlattices Nov. 03, 2020
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Patent Title: Semiconductor devices including hyper-abrupt junction region including a superlattice Nov. 03, 2020
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Patent Title: Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance Oct. 27, 2020
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Patent Title: Method for making superlattice structures with reduced defect densities Oct. 20, 2020
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Patent Title: Semiconductor device including enhanced contact structures having a superlattice Sep. 15, 2020
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Patent Title: Inverted t channel field effect transistor (itfet) including a superlattice Sep. 01, 2020
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Patent Title: Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface Aug. 11, 2020
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Patent Title: Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice Jul. 28, 2020
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Patent Title: Semiconductor device including superlattice structures with reduced defect densities Feb. 18, 2020
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Patent Title: Method for making cmos image sensor including pixels with read circuitry having a superlattice Jan. 07, 2020
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Patent Title: Cmos image sensor including pixels with read circuitry having a superlattice Jan. 07, 2020
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Patent Title: Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice Nov. 05, 2019
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Patent Title: Method for making cmos image sensor including photodiodes with overlying superlattices to reduce crosstalk Oct. 29, 2019
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Patent Title: Semiconductor device including resonant tunneling diode structure having a superlattice Oct. 22, 2019
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Patent Title: Semiconductor device including a superlattice as a gettering layer Sep. 10, 2019
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Patent Title: Method for making cmos image sensor with buried superlattice layer to reduce crosstalk Aug. 27, 2019
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Patent Title: Method for making a semiconductor device including a superlattice as a gettering layer Aug. 13, 2019
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Patent Title: Semiconductor device with recessed channel array transistor (rcat) including a superlattice Jul. 30, 2019
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