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Synopsys Inc

SNPS

SNPS: Synopsys is a provider of electronic design automation software, intellectual property, and software integrity products. EDA software automates the chip design process, enhancing design accuracy, productivity, and complexity in a full-flow end-to-end solution. The firm's growing SI business allows customers to continuously manage and test the code base for security and quality. Synopsys' comprehensive portfolio is benefiting from a mutual convergence of semiconductor companies moving up-stack toward systems-like companies, and systems companies moving down-stack toward in-house chip design. The resulting expansion in EDA customers alongside secular digitalization of various end markets benefits EDA vendors like Synopsys.

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Government lobbying spending instances

  • $60,000 Jul 20, 2023 Issue: Taxation/Internal Revenue Code Computer Industry Budget/Appropriations
  • $60,000 Jul 04, 2023 Issue: Defense
  • $20,000 Apr 20, 2023 Issue: Taxation/Internal Revenue Code Computer Industry Budget/Appropriations
  • $120,000 Apr 08, 2023 Issue: Defense
  • $40,000 Jan 09, 2023 Issue: Defense
  • $20,000 Jan 20, 2016 Issue: Homeland Security Consumer Issues/Safety/Products Computer Industry Science/Technology
  • $10,000 Jul 20, 2009 Issue: Taxation/Internal Revenue Code
  • $10,000 Jul 20, 2009 Issue: Taxation/Internal Revenue Code
U.S. Patents

New patents grants

  • Patent Title: Epitaxial growth of source and drain materials in a complementary field effect transistor (cfet) Aug. 29, 2023
  • Patent Title: Reinforcement learning-based adjustment of digital circuits Aug. 29, 2023
  • Patent Title: Prioritized mask correction Aug. 29, 2023
  • Patent Title: Localization of multiple scan chain defects per scan chain Aug. 29, 2023
  • Patent Title: Visual representation to assess quality of input stimulus in transistor-level circuits Aug. 22, 2023
  • Patent Title: Circuit layout verification Aug. 22, 2023
  • Patent Title: Memory efficient and scalable approach to stimulus (waveform) reading Aug. 22, 2023
  • Patent Title: System and method to process a virtual partition cell injected into a hierarchical integrated circuit design Aug. 22, 2023
  • Patent Title: Under test pin location driven simultaneous signal grouping and pin assignment Aug. 15, 2023
  • Patent Title: Waveform based reconstruction for emulation Aug. 15, 2023
  • Patent Title: Mask synthesis using design guided offsets Aug. 08, 2023
  • Patent Title: Automated method to check electrostatic discharge effect on a victim device Aug. 01, 2023
  • Patent Title: Fabrication technique for forming ultra-high density integrated circuit components Jul. 25, 2023
  • Patent Title: Automatic sequential retry on compilation failure Jul. 25, 2023
  • Patent Title: Automated balanced global clock tree synthesis in multi level physical hierarchy Jul. 18, 2023
  • Patent Title: Hardware based cyclic redundancy check (crc) re-calculator for timestamped frames over a data bus Jul. 18, 2023
  • Patent Title: Three-dimensional mask simulations based on feature images Jul. 18, 2023
  • Patent Title: Fast topology bus router for interconnect planning Jul. 04, 2023
  • Patent Title: Reformatting scan patterns in presence of hold type pipelines Jul. 04, 2023
  • Patent Title: Latency offset in pre-clock tree synthesis modeling Jun. 20, 2023
  • Patent Title: On-the-fly multi-bit flip flop generation Jun. 20, 2023
  • Patent Title: Interconnect repeater planning and implementation flow for abutting designs Jun. 13, 2023
  • Patent Title: Automatic test pattern generation (atpg) for parametric faults Jun. 06, 2023
  • Patent Title: Sequential delay enabler timer circuit for low voltage operation for srams Jun. 06, 2023
  • Patent Title: Application-specific integrated circuit (asic) synthesis based on lookup table (lut) mapping and optimization Jun. 06, 2023
  • Patent Title: Timing modeling of multi-stage cells using both behavioral and structural models May. 30, 2023
  • Patent Title: Classification of patterns in an electronic circuit layout using machine learning based encoding May. 30, 2023
  • Patent Title: High-speed functional protocol based test and debug May. 30, 2023
  • Patent Title: Tuning analog front end response for jitter tolerance margins May. 30, 2023
  • Patent Title: Construction, modeling, and mapping of multi-output cells May. 23, 2023
  • Patent Title: Wafer sensitivity determination and communication May. 23, 2023
  • Patent Title: Multi-port—multi mode reed solomon decoder May. 23, 2023
  • Patent Title: Independent skew control of a multi-phase clock May. 16, 2023
  • Patent Title: Glitch source identification and ranking May. 16, 2023
  • Patent Title: Dose optimization techniques for mask synthesis tools May. 16, 2023
  • Patent Title: Low latency decoder for error correcting codes May. 16, 2023
  • Patent Title: Selecting a subset of training data from a data pool for a power prediction model May. 16, 2023
  • Patent Title: Obtaining a mask using a cost function gradient from a jacobian matrix generated from a perturbation look-up table May. 09, 2023
  • Patent Title: Inverse etch model for mask synthesis May. 09, 2023
  • Patent Title: Source mask optimization by process defects prediction May. 02, 2023
  • Patent Title: Single flux quantum inverter circuit May. 02, 2023
  • Patent Title: Asynchronous chip-to-chip communication May. 02, 2023
  • Patent Title: Performance tuning of a hardware description language simulator Apr. 25, 2023
  • Patent Title: Machine learning-based algorithm to accurately predict detail-route drvs for efficient design closure at advanced technology nodes Apr. 25, 2023
  • Patent Title: Integrated circuit analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure Apr. 18, 2023
  • Patent Title: Packetized power-on-self-test controller for built-in self-test Apr. 11, 2023
  • Patent Title: Input schmitt buffer operating at a high voltage using low voltage devices Apr. 04, 2023
  • Patent Title: Transistor—level defect coverage and defect simulation Apr. 04, 2023
  • Patent Title: Pattern based die connector assignment using machine learning image recognition Apr. 04, 2023
  • Patent Title: Logic simulation of circuit designs using on-the-fly bit reduction for constraint solving Mar. 28, 2023
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