Arteris, Inc. Common Stock
AIP
AIP: Arteris Inc is a developer of on-chip interconnect fabric technology designed for a variety of devices and in the development and distribution of Network-on-Chip (NoC) interconnect intellectual property (IP). The company's technology is used in System-on-Chip (SoC) and provides software and services to automate SoC integration, enabling users to efficiently deploy NoC IP, and offer IP support, maintenance services, professional services, and training and on-site support services.
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Patent Title: Broadcast switch system in a network-on-chip (noc) Aug. 15, 2023
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Patent Title: Optimization of parameters for synthesis of a topology using a discriminant function module Jun. 13, 2023
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Patent Title: System and method for synthesis of a network-on-chip for deadlock-free transformation May. 30, 2023
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Patent Title: Multi-phase topology synthesis of a network-on-chip (noc) May. 23, 2023
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Patent Title: System and method for generation of quality metrics for optimization tasks in topology synthesis of a network Mar. 07, 2023
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Patent Title: System and method for generating and using a context block based on system parameters Feb. 07, 2023
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Patent Title: System and method for generating and using physical roadmaps in network synthesis Jan. 17, 2023
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Patent Title: System and method for configurable cache ip with flushable address range Jan. 17, 2023
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Patent Title: System and method for using a directory to recover a coherent system from an uncorrectable error Nov. 29, 2022
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Patent Title: Method for using victim buffer in cache coherent systems Nov. 22, 2022
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Patent Title: Queue management system, starvation and latency management system, and methods of use Nov. 01, 2022
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Patent Title: Synthesis of a network-on-chip (noc) using performance constraints and objectives Sep. 20, 2022
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Patent Title: System and method for transaction broadcast in a network on chip Sep. 06, 2022
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Patent Title: System and method for synthesis of a network-on-chip to determine optimal path with load balancing Aug. 16, 2022
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Patent Title: System and method for logic functional redundancy Aug. 16, 2022
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Patent Title: Generation of hardware design using a constraint solver module for topology synthesis Aug. 09, 2022
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Patent Title: System for memory access bandwidth management using ecc Jul. 12, 2022
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Patent Title: System and method for using soft lock with virtual channels in a network-on-chip (noc) Jun. 21, 2022
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Patent Title: System and method for advanced detection of failures in a network-on-chip Apr. 05, 2022
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Patent Title: Optimization of parameters for synthesis of a topology using a discriminant function module Mar. 22, 2022
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Patent Title: Configurable snoop filters for cache coherent systems Feb. 01, 2022
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Patent Title: System and method for interface protection Dec. 28, 2021
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Patent Title: Detection and isolation of faults to prevent propagation of faults in a resilient system Nov. 16, 2021
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Patent Title: Physically aware topology synthesis of a network Sep. 14, 2021
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Patent Title: System and method for estimation of chip floorplan activity Aug. 24, 2021
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Patent Title: System and method for computational transport network-on-chip (noc) Aug. 03, 2021
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Patent Title: Configurable snoop filters for cache coherent systems Aug. 03, 2021
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Patent Title: System and method for incremental topology synthesis of a network-on-chip Apr. 27, 2021
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Patent Title: System and method for predicting performance, power and area behavior of soft ip components in integrated circuit design Mar. 16, 2021
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Patent Title: System and method for isolating faults in a resilient system Jan. 26, 2021
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Patent Title: Recovery of a coherent system in the presence of an uncorrectable error Dec. 29, 2020
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Patent Title: System and method for reducing ecc overhead and memory access bandwidth Dec. 15, 2020
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Patent Title: System and method for designing a chip floorplan using machine learning Oct. 13, 2020
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Patent Title: Synthesizing topology for an interconnect network of a system-on-chip with intellectual property blocks Jul. 21, 2020
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Patent Title: Protection scheme conversion Jan. 07, 2020
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Patent Title: Control and address redundancy in storage buffer Nov. 26, 2019
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Patent Title: Redundancy for cache coherence systems Oct. 22, 2019
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Patent Title: System to reduce directory information storage Oct. 22, 2019
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Patent Title: Directory storage control for commonly used patterns Oct. 22, 2019
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Patent Title: Estimation of chip floorplan activity distribution Oct. 01, 2019
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Patent Title: Dynamic link serialization in network-on-chip Jun. 25, 2019
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Patent Title: Editing a noc topology on top of a floorplan Apr. 23, 2019
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Patent Title: Victim buffer for cache coherent systems Apr. 09, 2019
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Patent Title: Recovery of a system directory after detection of uncorrectable error Dec. 04, 2018
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Patent Title: Proxy cache conditional allocation Nov. 20, 2018
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Patent Title: Redundancy for cache coherence systems Jul. 17, 2018
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Patent Title: Editing a noc topology on top of a floorplan Apr. 10, 2018
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Patent Title: Automatic architecture placement guidance Dec. 26, 2017
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Patent Title: Network-on-chip (noc) topology generation Nov. 21, 2017
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Patent Title: Estimation of chip floorplan activity distribution Jul. 18, 2017
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