SHENZHEN, China, May 21, 2026 (GLOBE NEWSWIRE) -- MicroCloud Hologram Inc. (NASDAQ: HOLO), (“HOLO” or the "Company"), a technology service provider, proposed the engineering concept of digital qubits. Unlike physical qubits that rely on physical properties such as superposition states and entanglement states, digital qubits express the amplitude and phase evolution of wave functions through digital logic structures in FPGA, with their operation process strictly following the mathematical description of quantum mechanics. HOLO released a milestone technology—the hierarchical IP core generator for quantum Fourier transform implementation in FPGA. This technology revolves around one of the most critical foundational operators in quantum computing—the Quantum Fourier Transform (QFT). Through this technical scheme, quantum gate operations, state evolution, and measurement processes can be mapped to synthesizable VHDL modules, thereby building a repeatable, verifiable, and scalable quantum computing execution environment on FPGA.

Among numerous quantum algorithms, Shor's factorization algorithm is widely considered one of the most representative applications, with its core advantage stemming from the exponential acceleration capability of the quantum Fourier transform in the period-finding process. However, the engineering implementation of Shor's algorithm is highly dependent on the precision and scalability of QFT. To this end, in the early stage of HOLO's technology R&D, a systematic computational complexity estimation was first conducted on various quantum operations that must be executed in Shor's algorithm, building a complexity evaluation model oriented toward engineering implementation from multiple dimensions such as gate count, phase rotation precision, qubit scale, and control logic complexity.

This evaluation does not remain at the theoretical level but directly serves the design choices for the FPGA implementation path. Through complexity estimation, HOLO clarified the consumption trends of FPGA resources by the QFT module under different qubit scales, including the usage of lookup tables (LUT), flip-flops (FF), DSP units, and on-chip memory resources. This laid a quantitative foundation for the subsequent design of the hierarchical IP core generator, enabling the generator to perform controllable trade-offs between performance, precision, and resource occupancy.

On this basis, HOLO proposed and implemented a multi-level VHDL description generator for quantum Fourier transform implementation. This generator is not a simple code template tool but a structured generation system with algorithm understanding capabilities. Its core idea is to perform three-layer mapping of the mathematical structure of QFT, quantum circuit structure, and FPGA hardware structure, and build automated generation logic on top of this.

At the top layer, the generator takes quantum algorithm-level descriptions as input and can recognize algorithm parameters such as the number of qubits required for the target QFT, rotation gate precision, and whether to enable approximate QFT. This layer corresponds to the algorithm abstraction layer, primarily responsible for transforming the mathematical definition of the quantum Fourier transform into an executable quantum gate sequence.

At the intermediate layer, the generator maps the quantum gate sequence to logic structure modules, including controlled phase rotation modules, Hadamard modules, swap networks, and control paths. This layer is the key to the entire system; it not only needs to ensure the logical correctness of the quantum circuit but also must fully consider the parallel characteristics, pipeline structure, and timing constraints of FPGA. Through modular decomposition and parameterized design, the generator can support QFT implementations with different scales and precision requirements within the same framework.

To ensure the correctness and reliability of the generated IP cores, HOLO's this technology system also integrates an automated test circuit generation mechanism. The generator, while outputting the QFT coprocessor description, synchronously generates corresponding test circuits and test vectors. These test circuits can run in an FPGA simulation environment to verify key quantum state evolution results and perform comparative analysis with theoretical quantum Fourier transform results. This mechanism greatly lowers the threshold for quantum hardware verification, enabling R&D personnel to conduct systematic research on the execution process of complex quantum algorithms without requiring a real quantum computer.

From the perspective of enterprise engineering practice, this hierarchical IP core generator significantly improves the conversion efficiency of quantum algorithms from theory to hardware. In traditional methods, every change in quantum circuit scale may mean a large amount of manual VHDL modifications and re-verification, whereas this generator achieves one-time development and multi-scale reuse through parameterized and hierarchical design. This not only reduces R&D costs but also lays a universal foundation for subsequently supporting more quantum algorithm modules.

From a broader industrial perspective, this technology provides key infrastructure for building scalable quantum computing coprocessing platforms. Digital quantum coprocessors implemented through FPGA can serve as important components of quantum cloud platforms, quantum algorithm verification environments, and quantum software-hardware co-development platforms. Enterprises can utilize this technology to deploy quantum acceleration modules in existing data centers and embedded systems, thereby laying out quantum computing application ecosystems in advance without relying on large-scale physical quantum hardware.

This technology also has important significance in education, scientific research, and standardization. Through generatable and verifiable QFT IP cores, researchers can systematically study the behavioral characteristics of quantum algorithms under different hardware conditions, providing empirical data support for the architectural design of future real quantum computers. This progressive path from digital simulation to physical implementation is also considered a realistic choice for quantum computing toward engineering and industrialization.

HOLO's hierarchical IP core generator for quantum Fourier transform implementation in FPGA is not only a single-point technological innovation but also a systematized solution oriented toward future quantum computing engineering systems. By organically combining quantum mechanics descriptions, algorithm structures, and digital hardware design, it provides enterprises with a solid foundation for building controllable, scalable, and verifiable technical capabilities in the quantum computing era. As this technology continues to evolve and its application scenarios expand, its strategic value in the quantum computing industry chain will further manifest.

About MicroCloud Hologram Inc.

MicroCloud Hologram Inc. (NASDAQ: HOLO) is committed to the research and development and application of holographic technology. Its holographic technology services include holographic light detection and ranging (LiDAR) solutions based on holographic technology, holographic LiDAR point cloud algorithm architecture design, technical holographic imaging solutions, holographic LiDAR sensor chip design, and holographic vehicle intelligent vision technology, providing services to customers offering holographic advanced driving assistance systems (ADAS). MicroCloud Hologram Inc. provides holographic technology services to global customers. MicroCloud Hologram Inc. also provides holographic digital twin technology services and owns proprietary holographic digital twin technology resource libraries. Its holographic digital twin technology resource library utilizes a combination of holographic digital twin software, digital content, space data-driven data science, holographic digital cloud algorithms, and holographic 3D capture technology to capture shapes and objects in 3D holographic form. MicroCloud Hologram Inc. focuses on developments such as quantum computing and quantum holography, with cash reserves exceeding 3 billion RMB, and plans to invest more than 400 million in USD from the cash reserves to engage in blockchain development, quantum computing technology development, quantum holography technology development, and derivatives and technology development in frontier technology fields such as artificial intelligence AR. MicroCloud Hologram Inc.'s goal is to become a global leading quantum holography and quantum computing technology company.

Safe Harbor Statement

This press release contains forward-looking statements as defined by the Private Securities Litigation Reform Act of 1995. Forward-looking statements include statements concerning plans, objectives, goals, strategies, future events or performance, and underlying assumptions and other statements that are other than statements of historical facts. When the Company uses words such as "may," "will," "intend," "should," "believe," "expect," "anticipate," "project," "estimate," or similar expressions that do not relate solely to historical matters, it is making forward-looking statements. Forward-looking statements are not guarantees of future performance and involve risks and uncertainties that may cause the actual results to differ materially from the Company's expectations discussed in the forward-looking statements. These statements are subject to uncertainties and risks including, but not limited to, the following: the Company's goals and strategies; the Company's future business development; product and service demand and acceptance; changes in technology; economic conditions; reputation and brand; the impact of competition and pricing; government regulations; fluctuations in general economic; financial condition and results of operations; the expected growth of the holographic industry and business conditions in China and the international markets the Company plans to serve and assumptions underlying or related to any of the foregoing and other risks contained in reports filed by the Company with the Securities and Exchange Commission ("SEC"), including the Company's most recently filed Annual Report on Form 10-K and current report on Form 6-K and its subsequent filings. For these reasons, among others, investors are cautioned not to place undue reliance upon any forward-looking statements in this press release. Additional factors are discussed in the Company's filings with the SEC, which are available for review at www.sec.gov. The Company undertakes no obligation to publicly revise these forward-looking statements to reflect events or circumstances that arise after the date hereof.

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